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Formal Verification: An Essential Toolkit for Modern VLSI Design, by Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar
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Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
- Learn formal verification algorithms to gain full coverage without exhaustive simulation
- Understand formal verification tools and how they differ from simulation tools
- Create instant test benches to gain insight into how models work and find initial bugs
- Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems
- Sales Rank: #263348 in Books
- Published on: 2015-08-28
- Released on: 2015-08-14
- Original language: English
- Number of items: 1
- Dimensions: 9.25" h x .84" w x 7.50" l, 1.70 pounds
- Binding: Paperback
- 408 pages
Review
"...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification..." --VerificationAcademy.com
From the Back Cover
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
About the Author
Erik has worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. Currently he works in the Design Technology and Solutions division, where he supports formal verification usage for Intel teams worldwide. In his spare time he hosts the “Math Mutation” podcast, and serves as an elected director on the Hillsboro school board.
Tom recently joined the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.
Kiran has been working at intel India for past 11 years and has worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of verification including formal verification. Currently he leads the formal verification efforts for the graphics design in Visual Platform Group and supports formal verification at intel india site.
Most helpful customer reviews
1 of 1 people found the following review helpful.
Comprehensive Formal Methodology Based on Intel's 20 Year Deployment Experience
By Dan Benua
This book is targeted at RTL designers who want to become proficient with formal verification. It presents a staged adoption methodology starting from early design bring-up, through formal bug-hunting, to formal sign-off. In addition to traditional property checking, it also covers selected formal "Apps" including standard protocol checking, unreachable coverage, connectivity checking, and CSR verification. There is a chapter on equivalence checking, including sequential equivalence, and a chapter on complexity management detail several advanced abstraction techniques. Though most of the focus is on practical applications, there is also a chapter giving a high level description of BDD and SAT algorithms.
The discussions and examples are tool and vendor independent so this is not a replacement for tool-specific training. Many techniques are illustrated with code examples and waveforms that are complex enough to illustrate the methodology but also simple enough to follow without too much effort. The discussion starts at the beginning, assuming only knowledge of RTL design and simulation, but it progresses to advanced techniques that would benefit even expert-level readers.
I have been teaching formal verification tools and techniques to industrial practitioners for many years and I believe this book is the first to focus on adoption by designers and to present such a comprehensive methodology. I will certainly be recommending it to my customers and colleagues.
- Dan Benua
Formal Verification Tool Support Engineer
3 of 4 people found the following review helpful.
A MUST HAVE BOOK!
By benjamin cohen
The subtitle of this book, "Essential Toolkit for Modern VLSI Design", has definitely met its mark, and more! This is because the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation. I particularly appreciated many aspects of this book, including:
1. The maturity derived from extensive years of work experiences, with successes and pitfalls.
2. The organization and presentation of the subject matters, including the progression of knowledge being presented for easier absorption of the topics.
3. The practical tips derived from actual usage of formal verification and from real designs.
4. The various approaches, or angles of attack, in using formal verification when verifying different types of designs and situations.
5. The test case examples, and progression of solutions in achieving the end goals.
In summary, I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification; I certainly learned a lot from it!
Ben Cohen,
SystemVerilog Assertions specialist
1 of 1 people found the following review helpful.
Excellent book
By yoav karmon
An excellent and comprehensive overview of formal verification. This book is very well organized with a lot of useful tips. The book may be helpful for both inexperienced and experienced engineers.
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